Root cause for the SPI Chip Select Line Going High During SPI Read and SPI Write Operation

TIMER_INTERRUPT_HANDLER

• AS shown in above figure to identify the root cause I have used two spare GPIO's SPI_WRITE and TIMER_INT
• The SPI_WRITE signal is driven low just before writing into the SPI FIFO and then the signal will be driven high after the write into SPI FIFO is completed
• Similarly the TIMER_INT GPIO is driven low when the Timer Interrupt Handler is entered and the same GPIO will be driven on exiting the Timer Interrupt Handler
• Now, one can easily understand from the timing diagram that the Timer Interrupt Handler is taking 52 uS. 
• Our SPI Clock operates at 1 MHz. The data is written to the FIFO using CPU as there is no DMA. The size of the SPI TX FIFO is 128 bytes.
• We can see that there are three bytes sent over SPI_MOSI line and then the Timer Interrupt Handler triggers and causes SPI_CS to go high.
• The SPI_CS goes high when there is no data in TX FIFO.
• So, to prevent this probably we have to figure out the best solutions like while writing to the FIFO whether we have to make it atomic, reduce the SPI Clock or write to the SPI FIFO at least 64 bytes atomically or figure out to reduce the Timer Interrupt Handler execution and so on...

Let me know your feedback on this post...!

SPI Issues Observed while testing with SPI Flash

Today I will describe one of the problem observed with SPI Flash.

The SPI Flash is connected to a PSoC4 based controller as shown below

Our write to a SPI Page is as follows

1. Write a 256-Byte Data to a given page (0x02, PA[23:16], PA[15:8], PA[7:0], D0, D1, ...., D255)
2. Check BIT0 in read status register and wait till BIT0 goes to zero. The status Register is read using the command (0x05, 0x00)
3. Now read back the data using following command (0x03, PA[23:16], PA[15:8], PA[7:0], D0, D1, ...., D255)
4. Compare the Data sent in Step.1 with Step.3. When read data is not same as written data then there is an issue either with Read or Write

Now, I thought of using a good debug tool Saleae. Attached the Analyzer to the SPI Lines.

When I check the SPI lines the chip select line goes low to high during a transfer. Hence the SPI Flash treats it as fresh new SPI Transfer.

 

As shown in above picture the green circle is the one where the SPI Transfer command started and then red circle is where the Chip Select went from low to high.

When I read the SPI Master Datasheet here it is PSoC4 based controller it says that as soon as the transmit FIFO goes empty the chip select will be driven high. When the Transmit FIFO is filled again then one can observe that the chip select going low. But, as far as for SPI Flash this is a new SPI transfer.

Now let me zoom in and show whether the chip select toggles during a read or write transfer

 

1. The MOSI Line has the following Data (0x03, 0x00, 0x13, 0x00, D0,D1, ......,D255)
2. This indicates that it's a SPI Read transaction
3. Once the chip select goes high and then low the first byte which is 0x7E is treated as SPI_Flash_Command.

The SPI Master Controller allows the Chip Select can be either hardware controller or software controlled. I quickly removed the chip select with hardware controlled option and controlling the chip select line using Firmware.

Voila!!!

The issue is not observed any more. Let me see if I can find out the root cause of the issue.