Today I will describe one of the problem observed with SPI Flash.
The SPI Flash is connected to a PSoC4 based controller as shown below
Our write to a SPI Page is as follows
When I check the SPI lines the chip select line goes low to high during a transfer. Hence the SPI Flash treats it as fresh new SPI Transfer.
Voila!!!
The issue is not observed any more. Let me see if I can find out the root cause of the issue.
The SPI Flash is connected to a PSoC4 based controller as shown below
Our write to a SPI Page is as follows
- Write a 256-Byte Data to a given page (0x02, PA[23:16], PA[15:8], PA[7:0], D0, D1, ...., D255)
- Check BIT0 in read status register and wait till BIT0 goes to zero. The status Register is read using the command (0x05, 0x00)
- Now read back the data using following command (0x03, PA[23:16], PA[15:8], PA[7:0], D0, D1, ...., D255)
- Compare the Data sent in Step.1 with Step.3. When read data is not same as written data then there is an issue either with Read or Write
When I check the SPI lines the chip select line goes low to high during a transfer. Hence the SPI Flash treats it as fresh new SPI Transfer.
As shown in above picture the green circle is the one where the SPI Transfer command started and then red circle is where the Chip Select went from low to high.
When I read the SPI Master Datasheet here it is PSoC4 based controller it says that as soon as the transmit FIFO goes empty the chip select will be driven high. When the Transmit FIFO is filled again then one can observe that the chip select going low. But, as far as for SPI Flash this is a new SPI transfer.
Now let me zoom in and show whether the chip select toggles during a read or write transfer
- The MOSI Line has the following Data (0x03, 0x00, 0x13, 0x00, D0,D1, ......,D255)
- This indicates that it's a SPI Read transaction
- Once the chip select goes high and then low the first byte which is 0x7E is treated as SPI_Flash_Command.
Voila!!!
The issue is not observed any more. Let me see if I can find out the root cause of the issue.
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