Wednesday, April 17, 2019

Root cause for the SPI Chip Select Line Going High During SPI Read and SPI Write Operation

TIMER_INTERRUPT_HANDLER
  • AS shown in above figure to identify the root cause I have used two spare GPIO's SPI_WRITE and TIMER_INT
  • The SPI_WRITE signal is driven low just before writing into the SPI FIFO and then the signal will be driven high after the write into SPI FIFO is completed
  • Similarly the TIMER_INT GPIO is driven low when the Timer Interrupt Handler is entered and the same GPIO will be driven on exiting the Timer Interrupt Handler
  • Now, one can easily understand from the timing diagram that the Timer Interrupt Handler is taking 52 uS. 
  • Our SPI Clock operates at 1 MHz. The data is written to the FIFO using CPU as there is no DMA. The size of the SPI TX FIFO is 128 bytes.
  • We can see that there are three bytes sent over SPI_MOSI line and then the Timer Interrupt Handler triggers and causes SPI_CS to go high.
  • The SPI_CS goes high when there is no data in TX FIFO.
  • So, to prevent this probably we have to figure out the best solutions like while writing to the FIFO whether we have to make it atomic, reduce the SPI Clock or write to the SPI FIFO at least 64 bytes atomically or figure out to reduce the Timer Interrupt Handler execution and so on...
Let me know your feedback on this post...!

No comments:

Post a Comment